The present invention relates generally to a method for manufacturing a semiconductor device having a vertical transistor, and more particularly to a method for manufacturing a semiconductor device having a vertical transistor which can stabilize manufacturing processes.
The integration level of a semiconductor device continues to increase, the area of a unit cell decreases when viewed from above. Methods for forming a transistor, a bit line, a word line, and a capacitor within a limited area have been researched due to the decreasing area of the unit cell.
A semiconductor device having a transistor in which a source area and a drain area are positioned up and down in an active region to define a vertical channel, have been proposed. Such a transistor will be hereinafter referred to as a “vertical transistor”.
In the vertical transistor a silicon pillar is formed by etching a semiconductor substrate using a hard mask made of a nitride layer as an etch mask, a gate is formed on the sidewall of a lower portion of the silicon pillar, a source area is formed in an upper portion of the silicon pillar over the gate, and a drain area is formed in the semiconductor substrate beneath the silicon pillar.
In the semiconductor device having the vertical transistor structured as described above, by decreasing a cell scheme from a conventional 8F2 to 4F2, a net die can be significantly increased. Further, in the semiconductor device having the vertical transistor, gate drivability can be improved because a surrounding gate is formed. In addition, the characteristics and the reliability of the semiconductor device having the vertical transistor can be ensured, even when the area of the transistor is decreased, because the length of the channel does not decrease.
While not illustrated and explained in detail, in the conventional art, when manufacturing the semiconductor device having the vertical transistor, the hard mask made of a nitride layer is employed as etch and polish barriers at least three times in the course of forming the silicon pillar and the gate. In order to secure a process margin, the nitride layer for the hard mask is formed to a thickness over 1,500 Å. However, presence of the thick nitride layer for the hard mask is problematic because both the nitride layer for the hard mask and the silicon pillar are likely to lean while conducting a process.
Further, in the conventional art, a polysilicon layer for the gate is deposited to fill a space having a great aspect ratio, and as a result voids are likely to be produced in the space. Due to this fact, the loss of the semiconductor substrate can be caused when etching the polysilicon layer, whereby the characteristics of the semiconductor device can deteriorate.
In addition, in the conventional art, because the polysilicon layer for the gate is likely to remain on the sidewall of the upper portion of the silicon pillar, a short circuit can occur between adjoining gates.